LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 497

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.5.1
The reset sequence is initiated by any of the following events:
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles
(see
However, the internal reset circuit of the S12XECRG cannot sequence out of current reset condition
without a running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6
additional SYSCLK cycles depending on the internal synchronization latency. After 128+n SYSCLK
cycles the RESET pin is released. The reset generator of the S12XECRG waits for additional 64 SYSCLK
cycles and then samples the RESET pin to determine the originating source.
vector will be fetched.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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Figure
Low level is detected at the RESET pin (External Reset).
Power on is detected.
Low voltage is detected.
Illegal Address Reset is detected (see S12XMMC Block Guide for details).
COP watchdog times out.
Clock monitor failure is detected and Self-Clock Mode was disabled (SCME=0).
(64 cycles after release)
11-21). Since entry into reset is asynchronous it does not require a running SYSCLK.
Description of Reset Operation
Sampled RESET Pin
External circuitry connected to the RESET pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic one within 64 SYSCLK cycles after the low drive is released.
1
1
1
0
COP Watchdog Reset
Reset Source
MC9S12XE-Family Reference Manual Rev. 1.23
Reset Pending
Clock Monitor
Table 11-17. Reset Vector Selection
Table 11-16. Reset Summary
X
0
1
0
Reset Pending
NOTE
COP
X
X
0
1
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
COPCTL (CR[2:0] nonzero)
Illegal Address Reset/ External Reset
Local Enable
with rise of RESET pin
Illegal Address Reset/
Clock Monitor Reset
External Reset
Vector Fetch
POR / LVR /
POR / LVR /
COP Reset
Table 11-17
shows which
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