LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 177

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
1. Read: Anytime.
2.3.100 Port L Routing Register (PTLRR)
This register configures the re-routing of SCI7, SCI6, SCI5, and SCI4 on alternative ports.
2.3.101 Port F Data Register (PTF)
Freescale Semiconductor
Function
Address 0x0377
Address 0x0378
Write: Anytime.
Write: Anytime.
Altern.
Reset
Reset
W
W
R
R
PTLRR7
(TXD3)
PTF7
0
0
7
7
= Unimplemented or Reserved
PTLRR6
(RXD3)
PTFT6
0
0
6
6
Module
Figure 2-98. Port L Routing Register (PTLRR)
SCI7
SCI6
SCI5
SCI4
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-99. Port F Data Register (PTF)
Table 2-95. Port L Routing Summary
PTLRR5
(SCL0)
PTF5
0
0
5
5
7
0
1
x
x
x
x
x
x
PTLRR
6
x
x
0
1
x
x
x
x
PTLRR4
(SDA0)
5
x
x
x
x
0
1
x
x
PTF4
0
0
4
4
4
0
1
x
x
x
x
x
x
TXD
PH3
PH1
PH7
PH5
PL7
PL5
PL3
PL1
Related Pins
(CS3)
PTF3
3
0
0
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
RXD
PH2
PH0
PH6
PH4
PL6
PL4
PL2
PL0
(CS2)
PTF2
0
0
0
2
2
Access: User read/write
Access: User read/write
(CS1)
PTF1
0
0
0
1
1
(CS0)
PTF0
0
0
0
0
0
177
(1)
(1)