LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 150

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.56
150
Address 0x0263
Write: Anytime.
DDRH
DDRH
RDRH
Field
Field
Reset
7-0
1
0
W
R
Port H data direction—
This register controls the data direction of pin 1.
The enabled SCI6 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 0.
The enabled SCI6 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
RDRH7
Port H Reduced Drive Register (RDRH)
0
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTH or PTIH registers, when changing the
DDRH register.
RDRH6
Table 2-51. DDRH Register Field Descriptions (continued)
0
6
Figure 2-54. Port H Reduced Drive Register (RDRH)
Table 2-52. RDRH Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
RDRH5
0
5
RDRH4
NOTE
0
4
Description
Description
RDRH3
3
0
RDRH2
0
2
Access: User read/write
Freescale Semiconductor
RDRH1
0
1
RDRH0
0
0
(1)