LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 132

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime.

Chapter 2 Port Integration Module (S12XEPIMV1)

Address 0x024C

Address 0x024D

Write: Anytime.

Port S pull device enable—Enable pull devices on input pins

These bits conﬁgure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect

if the pin is used as an output. Out of reset all pull devices are enabled.

1 Pull device enabled.

0 Pull device disabled.

Port S pull device select—Determine pull device polarity on input pins

This register selects whether a pull-down or a pull-up device is connected to the pin.

1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.

0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.

Port S Pull Device Enable Register (PERS)

Port S Polarity Select Register (PPSS)

Figure 2-31. Port S Pull Device Enable Register (PERS)

Figure 2-32. Port S Polarity Select Register (PPSS)

Table 2-30. PERS Register Field Descriptions

Table 2-31. PPSS Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Access: User read/write

Freescale Semiconductor