LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 824

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 23 Voltage Regulator (S12VREGL3V3V1)
23.3.2.3
The VREGAPICL register allows the configuration of the VREG_3V3 autonomous periodical interrupt
features.
824
0x02F2
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
APICLK
Reset
APIES
APIEA
APIFE
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
LVDS
Field
Field
LVIE
LVIF
2
1
0
7
4
3
2
W
R
APICLK
Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
0 Input voltage V
1 Input voltage V
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
Note: On entering the Reduced Power Mode the LVIF is not cleared by the VREG_3V3.
Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if
APIFE = 0; APICLK cannot be changed if APIFE is set by the same write operation.
0 Autonomous periodical interrupt clock used as source.
1 Bus clock used as source.
Autonomous Periodical Interrupt External Select Bit — Selects the waveform at the external pin.If set, at the
external pin a clock is visible with 2 times the selected API Period
be a high pulse at the end of every selected period with the size of half of the min period
level specification for connectivity.
0 At the external periodic high pulses are visible, if APIEA and APIFE is set.
1 At the external pin a clock is visible, if APIEA and APIFE is set.
Autonomous Periodical Interrupt External Access Enable Bit — If set, the waveform selected by bit APIES
can be accessed externally. See device level specification for connectivity.
0 Waveform selected by APIES can not be accessed externally.
1 Waveform selected by APIES can be accessed externally, if APIFE is set.
Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer
when set.
0 Autonomous periodical interrupt is disabled.
1 Autonomous periodical interrupt is enabled and timer starts running.
Autonomous Periodical Interrupt Control Register (VREGAPICL)
0
7
Figure 23-4. Autonomous Periodical Interrupt Control Register (VREGAPICL)
= Unimplemented or Reserved
0
0
6
DDA
DDA
MC9S12XE-Family Reference Manual , Rev. 1.23
is above level V
is below level V
Table 23-5. VREGAPICL Field Descriptions
Table 23-4. VREGCTRL Field Descriptions
5
0
0
LVIA
LVID
and FPM.
or RPM or shutdown mode.
APIES
0
4
Description
Description
APIEA
0
3
(Table
APIFE
23-9). If not set, at the external pin will
2
0
Freescale Semiconductor
(Table
APIE
0
1
23-9). See device
APIF
0
0