LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 583

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
15.3
This section provides a detailed description of all memory and registers for the IIC module.
15.3.1
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
15.3.1.1
Read and write anytime
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Register
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
IBCR2
Name
IBCR
IBDR
IBAD
IBFD
IBSR
W
R
Module Base +0x0000
Memory Map and Register Definition
Register Descriptions
ADR7
IIC Address Register (IBAD)
0
7
W
W
W
W
W
W
R
R
R
R
R
R
= Unimplemented or Reserved
GCEN
ADR7
ADR6
IBEN
Bit 7
IBC7
TCF
D7
0
6
Figure 15-3. IIC Bus Address Register (IBAD)
MC9S12XE-Family Reference Manual Rev. 1.23
ADTYPE
= Unimplemented or Reserved
ADR6
Figure 15-2. IIC Register Summary
IBC6
IAAS
IBIE
D6
6
ADR5
5
0
MS/SL
ADR5
IBC5
IBB
D5
5
0
ADR4
0
4
ADR4
Tx/Rx
IBC4
IBAL
D4
4
0
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
ADR3
0
3
ADR3
TXAK
IBC3
D3
3
0
0
ADR2
ADR10
2
0
ADR2
IBC2
RSTA
SRW
D2
2
0
ADR1
ADR1
ADR9
IBC1
IBIF
D1
0
1
1
0
IBSWAI
RXAK
ADR8
Bit 0
IBC0
D0
0
0
0
0
583

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