LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 1190

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2)
Valid margin level settings for the Set Field Margin Level command are defined in
29.4.2.15 Full Partition D-Flash Command
The Full Partition D-Flash command allows the user to allocate sectors within the D-Flash block for
applications and a partition within the buffer RAM for EEPROM access. The D-Flash block consists of
128 sectors with 256 bytes per sector.
1190
FERSTAT
Register
FSTAT
Field margin levels must only be used during verify of the initial factory
programming.
Field margin levels can be used to check that Flash memory contents have
adequate margin for data retention at the normal level setting. If unexpected
results are encountered when checking Flash memory contents at field
margin levels, the Flash memory contents should be erased and
reprogrammed.
MGSTAT1
MGSTAT0
EPVIOLIF
ACCERR
Table 29-62. Set Field Margin Level Command Error Handling
Error Bit
FPVIOL
1. Read margin to the erased state
2. Read margin to the programmed state
(CCOBIX=001)
Table 29-61. Valid Set Field Margin Level Settings
0x0000
0x0001
0x0002
0x0003
0x0004
CCOB
MC9S12XE-Family Reference Manual , Rev. 1.23
Set if CCOBIX[2:0] != 001 at command launch
Set if a Load Data Field command sequence is currently active
Set if command not available in current mode (see
Set if an invalid global address [22:16] is supplied
Set if an invalid margin level setting is supplied
None
None
None
None
CAUTION
NOTE
Return to Normal Level
User Margin-1 Level
User Margin-0 Level
Field Margin-1 Level
Field Margin-0 Level
Level Description
Error Condition
(1)
(2)
1
2
Table
29-30)
Table
Freescale Semiconductor
29-61.