LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 808

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 22 Timer Module (TIM16B8CV2) Block Description
For the description of PACLK please refer
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an
input clock to the timer counter. The change from one selected clock to the other happens immediately
after these bits are written.
22.3.2.16 Pulse Accumulator Flag Register (PAFLG)
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags
in the PAFLG register. Timer module or Pulse Accumulator must stay enabled (TEN=1 or PAEN=1) while
clearing these bits.
808
Module Base + 0x0021
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
R
0
0
7
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
because the ÷64 clock is generated by the timer prescaler.
PAMOD
CLK1
Unimplemented or Reserved
0
0
1
1
0
0
1
1
Figure 22-25. Pulse Accumulator Flag Register (PAFLG)
0
0
6
PEDGE
CLK0
MC9S12XE-Family Reference Manual Rev. 1.23
0
1
0
1
0
1
0
1
Table 22-20. Timer Clock Selection
5
0
0
Table 22-19. Pin Action
Use PACLK/65536 as timer counter clock frequency
Use PACLK/256 as timer counter clock frequency
Figure
Use timer prescaler clock as timer counter clock
Div. by 64 clock enabled with pin high level
Use PACLK as input to timer counter clock
Div. by 64 clock enabled with pin low level
NOTE
22-30.
0
0
4
Timer Clock
Falling edge
Rising edge
Pin Action
0
0
3
2
0
0
Freescale Semiconductor
PAOVF
0
1
PAIF
0
0