LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 129

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
2.3.29
Freescale Semiconductor
Function
Address 0x0248
Write: Anytime.
Altern.
Field
Reset
PTS
PTS
PTS
PTS
PTS
PTS
7
6
5
4
3
2
W
R
Port S general purpose input/output data—Data Register
Port S pin 7 is associated with the SS signal of the SPI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port S general purpose input/output data—Data Register
Port S pin 6 is associated with the SCK signal of the SPI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port S general purpose input/output data—Data Register
Port S pin 5 is associated with the MOSI signal of the SPI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port S general purpose input/output data—Data Register
Port S pin 4 is associated with the MISO signal of the SPI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port S general purpose input/output data—Data Register
Port S pin 3 is associated with the TXD signal of the SCI1 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port S general purpose input/output data—Data Register
Port S bits 2 is associated with the RXD signal of the SCI1 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
PTS7
Port S Data Register (PTS)
SS0
0
7
PTST6
SCK0
0
6
Table 2-26. PTS Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-27. Port S Data Register (PTS)
MOSI0
PTS5
0
5
MISO0
PTS4
0
4
Description
TXD1
PTS3
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
RXD1
PTS2
0
2
Access: User read/write
TXD0
PTS1
0
1
RXD0
PTS0
0
0
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