LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 630

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
Module Base + 0x0018 to Module Base + 0x001B
1. Read: Anytime
Module Base + 0x0010 to Module Base + 0x0013
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
16.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see
“Identifier Registers
“Identifier Acceptance
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
630
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
AC[7:0]
Field
7-0
Figure 16-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
Figure 16-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
Reset
Reset
W
R
W
R
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
AC7
AC7
0
7
0
7
(IDR0–IDR3)”) of incoming messages in a bit by bit manner (see
Table 16-22. CANIDAR0–CANIDAR3 Register Field Descriptions
Filter”).
AC6
AC6
0
6
0
6
MC9S12XE-Family Reference Manual , Rev. 1.23
AC5
AC5
0
5
5
0
AC4
AC4
0
4
Description
0
4
AC3
AC3
0
3
3
0
AC2
AC2
0
2
0
2
Access: User read/write
Freescale Semiconductor
Access: User read/write
Section 16.3.3.1,
AC1
Section 16.4.3,
AC1
0
1
1
0
AC0
AC0
0
0
0
0
(1)
(1)