LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 267

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1.3
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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Run mode
This is the basic mode of operation.
Wait mode
In wait mode, the XINT module is frozen. It is however capable of either waking up the CPU if an
interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to
Section 6.5.3, “Wake Up from Stop or Wait Mode”
Stop Mode
In stop mode, the XINT module is frozen. It is however capable of either waking up the CPU if an
interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to
Section 6.5.3, “Wake Up from Stop or Wait Mode”
Freeze mode (BDM active)
In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please
refer to
Modes of Operation
Section 6.3.2.1, “Interrupt Vector Base Register (IVBR)”
MC9S12XE-Family Reference Manual Rev. 1.23
for details.
for details.
for details.
Chapter 6 Interrupt (S12XINTV2)
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