LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 770

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 21 Serial Peripheral Interface (S12SPIV5)
21.3.2.3
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
The baud rate divisor equation is as follows:
The baud rate can be calculated with the following equation:
770
Module Base +0x0002
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
SPPR[2:0]
SPR[2:0]
SPPR2
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
6–4
2–0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in
mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.
SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in
a change of these bits will abort a transmission in progress and force the SPI system into idle state.
Table 21-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 1 of 3)
SPI Baud Rate Register (SPIBR)
0
0
7
For maximum allowed baud rates, please refer to the SPI Electrical
Specification in the Electricals chapter of this data sheet.
SPPR1
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
SPPR2
0
6
Baud Rate = BusClock / BaudRateDivisor
BaudRateDivisor = (SPPR + 1) • 2
SPPR0
0
0
0
0
0
0
0
0
1
1
1
1
Figure 21-5. SPI Baud Rate Register (SPIBR)
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 21-6. SPIBR Field Descriptions
SPPR1
5
0
SPR2
0
0
0
0
1
1
1
1
0
0
0
0
SPPR0
NOTE
SPR1
0
4
0
0
1
1
0
0
1
1
0
0
1
1
Description
SPR0
(SPR + 1)
0
0
0
1
0
1
0
1
0
1
0
1
0
1
3
Baud Rate
SPR2
Divisor
2
0
128
256
16
32
64
16
32
2
4
8
4
8
Table
Freescale Semiconductor
SPR1
21-7. In master mode,
0
Table
1
1.5625 Mbit/s
1.5625 Mbit/s
781.25 kbit/s
390.63 kbit/s
195.31 kbit/s
781.25 kbit/s
3.125 Mbit/s
3.125 Mbit/s
97.66 kbit/s
Baud Rate
12.5 Mbit/s
6.25 Mbit/s
6.25 Mbit/s
21-7. In master
Eqn. 21-1
Eqn. 21-2
SPR0
0
0