ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 991

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

39.7
Table 39-8.
Note:
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
0x98 - 0xAC
0xC4 - 0xE0
0xEC - 0xF8
0x90 - 0x90
Offset
0x0C
0x1C
0x2C
0x3C
0x4C
0x8C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
0x40
0x44
0x48
0x50
0x54
0x94
0xE4
0xE8
0xFC
Analog-to-Digital Converter (ADC) User Interface
If an offset is not listed in the table it must be considered as “reserved”.
...
Register Mapping
Register
Control Register
Mode Register
Channel Sequence Register 1
Channel Sequence Register 2
Channel Enable Register
Channel Disable Register
Channel Status Register
Reserved
Last Converted Data Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Interrupt Status Register
Reserved
Reserved
Overrun Status Register
Extended Mode Register
Compare Window Register
Channel Gain Register
Channel Offset Register
Channel Data Register 0
Channel Data Register 1
...
Channel Data Register 15
Reserved
Analog Control Register
Reserved
Reserved
Write Protect Mode Register
Write Protect Status Register
Reserved
Reserved
Any offset not listed in
Table 39-8
must be considered as “reserved”.
ADC_SEQR1
ADC_SEQR2
ADC_CDR15
ADC_WPMR
ADC_WPSR
ADC_CHDR
ADC_CHSR
ADC_CHER
ADC_LCDR
ADC_OVER
ADC_CDR0
ADC_CDR1
ADC_CWR
ADC_EMR
ADC_CGR
ADC_COR
ADC_ACR
ADC_IMR
ADC_IER
ADC_IDR
ADC_ISR
ADC_MR
ADC_CR
Name
...
–
–
–
–
–
–
–
–
SAM3S Preliminary
SAM3S Preliminary
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Access
...
–
–
–
–
–
–
–
–
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000100
0x00000000
0x00000000
Reset
...
–
–
–
–
–
–
–
–
–
–
–
–
–
991
991