ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 94
![IC MCU 32BIT 64KB FLASH 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATSAM3S1BA-AU
Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S1BA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (24Mb)
10.12.4
10.12.4.1
10.12.4.2
10.12.4.3
10.12.4.4
10.12.4.5
94
STRBTEQ
LDRHT
SAM3S Preliminary
LDR and STR, unprivileged
Syntax
Operation
Restrictions
Condition flags
Examples
R4, [R7]
R2, [R2, #8]
Load and Store with unprivileged access.
where:
op
type is one of:
cond
Rt
Rn
offset
These load and store instructions perform the same function as the memory access instructions
with immediate offset, see
these instructions have only unprivileged access even when used in privileged software.
When used in unprivileged software, these instructions behave in exactly the same way as nor-
mal memory access instructions with immediate offset.
In these instructions:
These instructions do not change the flags.
• Rn must not be PC
• Rt must not be SP and must not be PC.
op{type}T{cond} Rt, [Rn {, #offset}]
LDR
STR
B
SB
H
SH
-
; Conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
; Load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access
is one of:
Load Register.
Store Register.
unsigned byte, zero extend to 32 bits on loads.
signed byte, sign extend to 32 bits (LDR only).
unsigned halfword, zero extend to 32 bits on loads.
signed halfword, sign extend to 32 bits (LDR only).
omit, for word.
is an optional condition code, see
is the register to load or store.
is the register on which the memory address is based.
is an offset from Rn and can be 0 to 255.
If offset is omitted, the address is the value in Rn.
“LDR and STR, immediate offset” on page
“Conditional execution” on page
; immediate offset
89. The difference is that
6500C–ATARM–8-Feb-11
84.
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