ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 718

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

• STTBRK: Start Break
0: No effect.
1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been trans-
mitted. No effect if a break is already being transmitted.
• STPBRK: Stop Break
0: No effect.
1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.
No effect if no break is being transmitted.
• STTTO: Start Time-out
0: No effect.
1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.
• SENDA: Send Address
0: No effect.
1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.
• RSTIT: Reset Iterations
0: No effect.
1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.
• RSTNACK: Reset Non Acknowledge
0: No effect
1: Resets NACK in US_CSR.
• RETTO: Rearm Time-out
0: No effect
1: Restart Time-out
• DTREN: Data Terminal Ready Enable
0: No effect.
1: Drives the pin DTR to 0.
• DTRDIS: Data Terminal Ready Disable
0: No effect.
1: Drives the pin DTR to 1.
• RTSEN: Request to Send Enable
0: No effect.
1: Drives the pin RTS to 0.
• FCS: Force SPI Chip Select
FCS = 0: No effect.
FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave
718
718
– Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE):
SAM3S Preliminary
SAM3S Preliminary
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11