ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 378
![IC MCU 32BIT 64KB FLASH 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATSAM3S1BA-AU
Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S1BA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Figure 23-14. Early Read Wait State: Write with No Hold Followed by Read with No Setup
378
SAM3S Preliminary
A[23:0]
D[7:0]
NWE
MCK
NRD
• if the write controlling signal has no hold time and the read controlling signal has no setup
• in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS
• in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD =
time
signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode
23-15). The write operation must end with a NCS rising edge. Without an Early Read Wait
State, the write operation could not complete properly.
0), the feedback of the write control signal is used to control address, data, and chip select
lines. If the external write control signal is not inactivated as expected due to load
capacitances, an Early Read Wait State is inserted and address, data and control signals are
maintained one more cycle. See
(Figure
write cycle
23-14).
no hold
Early Read
wait state
Figure
23-16.
no setup
read cycle
6500C–ATARM–8-Feb-11
(Figure
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