ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 806

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

35.8.4
806
SAM3S Preliminary
Write Operation
In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value
when writing non-multiple block size. If the bit PDCPADV is 0, then 0x00 value is used when
padding data, otherwise 0xFF is used.
If set, the bit PDCMODE enables PDC transfer.
The following flowchart
PDC facilities. Polling or interrupt method can be used to wait for the end of write according to
the contents of the Interrupt Mask Register (HSMCI_IMR).
(Figure
35-9) shows how to write a single block with or without use of
6500C–ATARM–8-Feb-11