ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 813

IC MCU 32BIT 64KB FLASH 64LQFP

ATSAM3S1BA-AU

Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Datasheets

Specifications of ATSAM3S1BA-AU

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S1BA-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATSAM3S1BA-AUR
Manufacturer:
Atmel
Quantity:
10 000
35.13 Write Protection Registers
6500C–ATARM–8-Feb-11
To prevent any single software error that may corrupt HSMCI behavior, the entire HSMCI
address space from address offset 0x000 to 0x00FC can be write-protected by setting the
WPEN bit in the
If a write access to anywhere in the HSMCI address space from address offset 0x000 to 0x00FC
is detected, then the WPVS flag in the HSMCI Write Protect Status Register (HSMCI_WPSR) is
set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the HSMCI Write Protect Mode Register (HSMCI_WPMR)
with the appropriate access key, WPKEY.
The protected registers are:
“HSMCI Mode Register” on page 816
“HSMCI Data Timeout Register” on page 818
“HSMCI SDCard/SDIO Register” on page 819
“HSMCI Completion Signal Timeout Register” on page 825
“” on page 838
“HSMCI Configuration Register” on page 839
“HSMCI Write Protect Mode Register”
(HSMCI_WPMR).
SAM3S Preliminary
813

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