ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 121

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.14.2
10.14.2.1
10.14.2.2
10.14.2.3
10.14.2.4
10.14.2.5
6500C–ATARM–8-Feb-11
UMULL
SMLAL
UMULL, UMLAL, SMULL, and SMLAL
Syntax
Operation
Restrictions
Condition flags
Examples
R0, R4, R5, R6
R4, R5, R3, R8
Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and pro-
ducing a 64-bit result.
where:
op
cond
RdHi, RdLo
Rn, Rm
The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies
these integers and places the least significant 32 bits of the result in RdLo, and the most signifi-
cant 32 bits of the result in RdHi.
The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies
these integers, adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo,
and writes the result back to RdHi and RdLo.
The SMULL instruction interprets the values from Rn and Rm as two’s complement signed inte-
gers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and
the most significant 32 bits of the result in RdHi.
The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed inte-
gers. It multiplies these integers, adds the 64-bit result to the 64-bit signed integer contained in
RdHi and RdLo, and writes the result back to RdHi and RdLo.
In these instructions:
These instructions do not affect the condition code flags.
• do not use SP and do not use PC
• RdHi and RdLo must be different registers.
op{cond} RdLo, RdHi, Rn, Rm
UMULL Unsigned Long Multiply.
UMLAL Unsigned Long Multiply, with Accumulate.
SMULL Signed Long Multiply.
SMLAL Signed Long Multiply, with Accumulate.
is one of:
is an optional condition code, see
are the destination registers.
For UMLAL and SMLAL they also hold the accumulating value.
are registers holding the operands.
; Unsigned (R4,R0) = R5 x R6
; Signed (R5,R4) = (R5,R4) + R3 x R8
“Conditional execution” on page
SAM3S Preliminary
84.
121