ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 442

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26.15 Write Protection Registers
To prevent any single software error that may corrupt PMC behavior, certain address spaces
can be write-protected by setting the WPEN bit in the
“PMC Write Protect Mode Register”
(PMC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PMC Write
Protect Status Register (PMC_WPSR) is set and the field WPVSRC indicates in which register
the write access has been attempted.
The WPVS flag is reset by writing the PMC Write Protect Mode Register (PMC_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
“PMC System Clock Enable Register” on page 444
“PMC System Clock Disable Register” on page 445
“PMC Peripheral Clock Enable Register 0” on page 447
“PMC Peripheral Clock Disable Register 0” on page 448
“PMC Clock Generator Main Oscillator Register” on page 450
“PMC Clock Generator PLLA Register” on page 453
“PMC Clock Generator PLLB Register” on page 454
“PMC Master Clock Register” on page 455
“PMC USB Clock Register” on page 456
“PMC Programmable Clock Register” on page 457
“PMC Fast Startup Mode Register” on page 463
“PMC Fast Startup Polarity Register” on page 464
“PMC Peripheral Clock Enable Register 1” on page 468
“PMC Peripheral Clock Disable Register 1” on page 469
“PMC Oscillator Calibration Register” on page 471
SAM3S Preliminary
442
6500C–ATARM–8-Feb-11