ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 590

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 30-8. PDC Status Register Flags Behavior
30.7.3.3
30.7.3.4
590
590
(from master)
(from slave)
TXEMPTY
SAM3S Preliminary
SAM3S Preliminary
RXBUFF
TXBUFE
ENDRX
ENDTX
NPCS0
SPCK
MOSI
MISO
Clock Generation
Transfer Delays
The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1
and 255.
This allows a maximum operating baud rate at up to Master Clock and a minimum operating
baud rate of MCK divided by 255.
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead
to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first
transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the
SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud
rate for each interfaced peripheral without reprogramming.
Figure 30-9
select. Three delays can be programmed to modify the transfer waveforms:
• The delay between chip selects, programmable only once for all the chip selects by writing
• The delay before SPCK, independently programmable for each chip select by writing the field
• The delay between consecutive transfers, independently programmable for each chip select
MSB
the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one
chip select and before assertion of a new one.
DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted.
by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on
the same chip select
MSB
6
6
5
5
shows a chip select transfer change and consecutive transfers on the same chip
4
4
1
3
3
2
2
1
1
LSB
LSB
MSB
MSB
6
6
5
5
4
4
2
3
3
2
2
1
1
LSB
LSB
MSB
MSB
6
6
5
5
3
4
4
3
3
2
2
1
1
LSB
LSB
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11