ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 284

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5.6
Name:
Address:
Access:
• SMEN: Supply Monitor Wake Up Enable
0 (NOT_ENABLE) = the supply monitor detection has no wake up effect.
1 (ENABLE) = the supply monitor detection forces the wake up of the core power supply.
• RTTEN: Real Time Timer Wake Up Enable
0 (NOT_ENABLE) = the RTT alarm signal has no wake up effect.
1 (ENABLE) = the RTT alarm signal forces the wake up of the core power supply.
• RTCEN: Real Time Clock Wake Up Enable
0 (NOT_ENABLE) = the RTC alarm signal has no wake up effect.
1 (ENABLE) = the RTC alarm signal forces the wake up of the core power supply.
• WKUPDBC: Wake Up Inputs Debouncer Period
284
31
23
15
–
–
–
7
–
Value
0
1
2
3
4
5
6
7
SAM3S Preliminary
Supply Controller Wake Up Mode Register
30
22
14
0x400E141C
–
–
6
–
SUPC_WUMR
Read-write
32768_SCLK
IMMEDIATE
4096_SCLK
512_SCLK
32_SCLK
Reserved
Reserved
3_SCLK
Name
WKUPDBC
29
21
13
–
–
5
–
Description
Immediate, no debouncing, detected active at least on one Slow Clock edge.
WKUPx shall be in its active state for at least 3 SLCK periods
WKUPx shall be in its active state for at least 32 SLCK periods
WKUPx shall be in its active state for at least 512 SLCK periods
WKUPx shall be in its active state for at least 4,096 SLCK periods
WKUPx shall be in its active state for at least 32,768 SLCK periods
Reserved
Reserved
28
20
12
–
–
4
–
RTCEN
27
19
11
–
–
–
3
RTTEN
26
18
10
–
–
–
2
SMEN
25
17
–
–
9
–
1
6500C–ATARM–8-Feb-11
24
16
–
–
8
–
0
–