ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 316

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.2.5.5
316
SAM3S Preliminary
Flash General-purpose NVM Commands
In the same way, the Clear Lock command (CLB) is used to clear lock bits.
Table 19-11. Set and Clear Lock Bit Command
Lock bits can be read using Get Lock Bit command (GLB). The n
n of the bit mask is set..
Table 19-12. Get Lock Bit Command
General-purpose NVM bits (GP NVM bits) can be set using the Set GPNVM command (SGPB).
This command also activates GP NVM bits. A bit mask is provided as argument to the com-
mand. When bit 0 of the bit mask is set, then the first GP NVM bit is activated.
In the same way, the Clear GPNVM command (CGPB) is used to clear general-purpose NVM
bits. The general-purpose NVM bit is deactivated when the corresponding bit in the pattern value
is set to 1.
Table 19-13. Set/Clear GP NVM Command
General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The n
GP NVM bit is active when bit n of the bit mask is set..
Table 19-14. Get GP NVM Bit Command
Step
1
2
Step
1
2
Step
1
2
Step
1
2
Handshake Sequence
Write handshaking
Write handshaking
Handshake Sequence
Write handshaking
Read handshaking
Handshake Sequence
Write handshaking
Write handshaking
Handshake Sequence
Write handshaking
Read handshaking
MODE[3:0]
CMDE
DATA
MODE[3:0]
CMDE
DATA
MODE[3:0]
CMDE
DATA
MODE[3:0]
CMDE
DATA
DATA[15:0] or DATA[7:0]
SLB or CLB
Bit Mask
DATA[15:0] or DATA[7:0]
GLB
Lock Bit Mask Status
0 = Lock bit is cleared
1 = Lock bit is set
DATA[15:0] or DATA[7:0]
SGPB or CGPB
GP NVM bit pattern value
DATA[15:0] or DATA[7:0]
GGPB
GP NVM Bit Mask Status
0 = GP NVM bit is cleared
1 = GP NVM bit is set
th
lock bit is active when the bit
6500C–ATARM–8-Feb-11
th