ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 500

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 28-3.
500
500
Offset
0x0070
0x0074
0x0078
to
0x007C
0x0080
0x0084
0x0088
0x008C
0x0090
0x0094
0x0098
0x009C
0x00A0
0x00A4
0x00A8
0x00AC
0x00B0
0x00B4
0x00B8
0x00BC
0x00C0
0x00C4
0x00C8
0x00CC
0x00D0
0x00D4
0x00D8
0x00DC
0x00E0
0x00E4
0x00E8
0x00EC
to
0x00F8
0x0100
0x0104-
0x010C
0x0110
0x0114-
0x011C
SAM3S Preliminary
SAM3S Preliminary
Register
Peripheral Select Register 1
Peripheral Select Register 2
Reserved
Input Filter Slow Clock Disable Register
Input Filter Slow Clock Enable Register
Input Filter Slow Clock Status Register
Slow Clock Divider Debouncing Register
Pad Pull-down Disable Register
Pad Pull-down Enable Register
Pad Pull-down Status Register
Reserved
Output Write Enable
Output Write Disable
Output Write Status Register
Reserved
Additional Interrupt Modes Enable Register
Additional Interrupt Modes Disables Register
Additional Interrupt Modes Mask Register
Reserved
Edge Select Register
Level Select Register
Edge/Level Status Register
Reserved
Falling Edge/Low Level Select Register
Rising Edge/ High Level Select Register
Fall/Rise - Low/High Status Register
Reserved
Lock Status
Write Protect Mode Register
Write Protect Status Register
Reserved
Schmitt Trigger Register
Reserved
Reserved
Reserved
Register Mapping (Continued)
Name
PIO_ABCDSR1
PIO_ABCDSR2
PIO_IFSCDR
PIO_IFSCSR
PIO_PPDSR
PIO_AIMMR
PIO_FRLHSR
PIO_LOCKSR
PIO_IFSCER
PIO_SCDR
PIO_PPDDR
PIO_PPDER
PIO_OWER
PIO_OWDR
PIO_OWSR
PIO_AIMER
PIO_AIMDR
PIO_ESR
PIO_LSR
PIO_ELSR
PIO_FELLSR
PIO_REHLSR
PIO_WPMR
PIO_WPSR
PIO_SCHMITT
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Access
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
0xFFFFFFFF
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
0x0
0x0
–
–
–
–
–
–
–
–
–
–
–
–