ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 98

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.12.6.3
10.12.6.4
10.12.6.5
10.12.6.6
98
LDM
STMDB
STM
LDM
SAM3S Preliminary
Restrictions
Condition flags
Examples
Incorrect examples
R8,{R0,R2,R9}
R1!,{R3-R6,R11,R12}
R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable
R2, {}
The accesses happen in order of decreasing register numbers, with the highest numbered regis-
ter using the highest memory address and the lowest number register using the lowest memory
address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn.
The PUSH and POP instructions can be expressed in this form. See
99
In these instructions:
When PC is in reglist in an LDM instruction:
These instructions do not change the flags.
• Rn must not be PC
• reglist must not contain SP
• in any STM instruction, reglist must not contain PC
• in any LDM instruction, reglist must not contain PC if it contains LR
• reglist must not contain Rn if you specify the writeback suffix.
• bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to
• if the instruction is conditional, it must be the last instruction in the IT block.
for details.
this halfword-aligned address
; There must be at least one register in the list
; LDMIA is a synonym for LDM
“PUSH and POP” on page
6500C–ATARM–8-Feb-11