ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 867

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

36.6.3
6500C–ATARM–8-Feb-11
PWM Comparison Units
The PWM provides 8 independent comparison units able to compare a programmed value with
the current value of the channel 0 counter (which is the channel counter of all synchronous
channels,
erate pulses on the event lines (used to synchronize ADC, see
Lines”), to generate software interrupts and to trigger PDC transfer requests for the synchronous
channels (see
update” on page
Figure 36-14. Comparison Unit Block Diagram
The comparison x matches when it is enabled by the bit CEN in the
Register”
the comparison value defined by the field CV in
(PWM_CMPxV for the comparison x). If the counter of the channel 0 is center aligned (CALG =
1 in
is made when the counter is counting up or counting down (in left alignment mode CALG=0, this
bit is useless).
If a fault is active on the channel 0, the comparison is disabled and cannot match (see
36.6.2.6 “Fault
The user can define the periodicity of the comparison x by the fields CTR and CPR (in
PWM_CMPxV). The comparison is performed periodically once every CPR+1 periods of the
counter of the channel 0, when the value of the comparison period counter CPRCNT (in
PWM_CMPxM) reaches the value defined by CTR. CPR is the maximum value of the compari-
son period counter CPRCNT. If CPR=CTR=0, the comparison is performed at each period of the
counter of the channel 0.
The comparison x configuration can be modified while the channel 0 is enabled by using the
“PWM Comparison x Mode Update Register”
x). In the same way, the comparison x value can be modified while the channel 0 is enabled by
using the
comparison x).
“PWM Channel Mode Register”
“PWM Comparison x Value Update Register”
Section 36.6.2.7 “Synchronous
(PWM_CMPxM for the comparison x) and when the counter of the channel 0 reaches
CEN [PWM_CMPxM]
fault on channel 0
CV [PWM_CMPxV]
CNT [PWM_CCNT0]
CNT [PWM_CCNT0] is decrementing
CVM [PWM_CMPxV]
CALG [PWM_CMR0]
CPRCNT [PWM_CMPxM]
CTR [PWM_CMPxM]
Protection”).
“Method 3: Automatic write of duty-cycle values and automatic trigger of the
864).
), the bit CVM (in PWM_CMPxV) defines if the comparison
Channels”). These comparisons are intended to gen-
=
=
=
(PWM_CMPxMUPD registers for the comparison
1
0
1
“PWM Comparison x Value Register”
(PWM_CMPxVUPD registers for the
SAM3S Preliminary
Section 36.6.4 “PWM Event
“PWM Comparison x Mode
Comparison x
Section
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