ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 510

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

28.7.17
Name:
Addresses:
Access:
• P0-P31: Input Change Interrupt Status
0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
28.7.18
Name:
Addresses:
Access:
This register can only be written if the WPEN bit is cleared in
• P0-P31: Multi Drive Enable.
0 = No effect.
1 = Enables Multi Drive on the I/O line.
510
510
P31
P23
P15
P31
P23
P15
P7
P7
31
23
15
31
23
15
7
7
SAM3S Preliminary
SAM3S Preliminary
PIO Interrupt Status Register
PIO Multi-driver Enable Register
P30
P22
P14
P30
P22
P14
P6
P6
30
22
14
30
22
14
PIO_ISR
0x400E0E4C (PIOA), 0x400E104C (PIOB), 0x400E124C (PIOC)
Read-only
6
PIO_MDER
0x400E0E50 (PIOA), 0x400E1050 (PIOB), 0x400E1250 (PIOC)
Write-only
6
P13
P13
P29
P21
P29
P21
P5
P5
29
21
13
29
21
13
5
5
P28
P20
P12
P28
P20
P12
P4
P4
28
20
12
28
20
12
4
4
“PIO Write Protect Mode Register”
P11
P11
P27
P19
P27
P19
P3
P3
27
19
11
27
19
11
3
3
P26
P18
P10
P26
P18
P10
P2
P2
26
18
10
26
18
10
2
2
.
P25
P17
P25
P17
P9
P1
P9
P1
25
17
25
17
9
1
9
1
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
P24
P16
P24
P16
P8
P0
P8
P0
24
16
24
16
8
0
8
0