ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 167

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.21.4
• PENDSVSET
RW
PendSV set-pending bit.
Write:
0 = no effect
1 = changes PendSV exception state to pending.
Read:
0 = PendSV exception is not pending
1 = PendSV exception is pending.
Writing 1 to this bit is the only way to set the PendSV exception state to pending.
• PENDSVCLR
WO
PendSV clear-pending bit.
Write:
0 = no effect
1 = removes the pending state from the PendSV exception.
6500C–ATARM–8-Feb-11
Reserved for
Reserved
Debug
31
23
15
7
Interrupt Control and State Register
ISRPENDING
30
22
14
6
VECTPENDING
Reserved
The ICSR:
See the register summary in
on page
• provides:
• indicates:
– set-pending and clear-pending bits for the PendSV and SysTick exceptions
– the exception number of the exception being processed
– whether there are preempted active exceptions
– the exception number of the highest priority pending exception
– whether any interrupts are pending.
191, for the ICSR attributes. The bit assignments are:
29
21
13
5
PENDSVSET
28
20
12
4
VECTACTIVE
Table 10-30 on page
PENDSVCLR
RETTOBASE
27
19
11
3
VECTPENDING
164, and the Type descriptions in
PENDSTSET
26
18
10
2
SAM3S Preliminary
Reserved
PENDSTCLR
25
17
9
1
VECTACTIVE
Table 10-33
Reserved
24
16
8
0
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