ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 870

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

36.6.5
36.6.5.1
870
SAM3S Preliminary
PWM Controller Operations
Initialization
Before enabling the channels, they must have been configured by the software application:
• Unlock User Interface by writing the WPCMD field in the PWM_WPCR Register.
• Configuration of the clock generator (DIVA, PREA, DIVB, PREB in the PWM_CLK register if
• Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
• Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx
• Selection of the counter event selection (if CALG = 1) for each channel (CES field in the
• Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx
• Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in
• Configuration of the duty-cycle for each channel (CDTY in the PWM_CDTYx register).
• Configuration of the dead-time generator for each channel (DTH and DTL in PWM_DTx) if
• Selection of the synchronous channels (SYNCx in the PWM_SCM register)
• Selection of the moment when the WRDY flag and the corresponding PDC transfer request
• Configuration of the update mode (UPDM in the PWM_SCM register)
• Configuration of the update period (UPR in the PWM_SCUP register) if needed.
• Configuration of the comparisons (PWM_CMPxV and PWM_CMPxM).
• Configuration of the event lines (PWM_ELxMR).
• Configuration of the fault inputs polarity (FPOL in PWM_FMR)
• Configuration of the fault protection (FMOD and FFIL in PWM_FMR, PWM_FPV and
• Enable of the Interrupts (writing CHIDx and FCHIDx in PWM_IER1 register, and writing
• Enable of the PWM channels (writing CHIDx in the PWM_ENA register)
required).
register)
PWM_CMRx register)
register)
PWM_CPRDx register is possible while the channel is disabled. After validation of the
channel, the user must use PWM_CPRDUPDx register to update PWM_CPRDx as
explained below.
Writing in PWM_CDTYx register is possible while the channel is disabled. After validation of
the channel, the user must use PWM_CDTYUPDx register to update PWM_CDTYx as
explained below.
enabled (DTE bit in the PWM_CMRx register). Writing in the PWM_DTx register is possible
while the channel is disabled. After validation of the channel, the user must use
PWM_DTUPDx register to update PWM_DTx
are set (PTRM and PTRCS in the PWM_SCM register)
PWM_FPE1)
WRDYE, ENDTXE, TXBUFE, UNRE, CMPMx and CMPUx in PWM_IER2 register)
6500C–ATARM–8-Feb-11