ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 90

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.12.2.5
10.12.2.6
10.12.2.7
90
SAM3S Preliminary
Post-indexed addressing
Restrictions
Condition flags
The address obtained from the register Rn is used as the address for the memory access. The
offset value is added to or subtracted from the address, and written back into the register Rn.
The assembly language syntax for this mode is:
The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can
either be signed or unsigned. See
Table 10-18
Table 10-18. Offset ranges
For load instructions:
When Rt is PC in a word load instruction:
For store instructions:
These instructions do not change the flags.
Instruction type
Word, halfword, signed
halfword, byte, or signed
byte
Two words
• Rt can be SP or PC for word loads only
• Rt must be different from Rt2 for two-word loads
• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
• bit[0] of the loaded value must be 1 for correct execution
• a branch occurs to the address created by changing bit[0] of the loaded value to 0
• if the instruction is conditional, it must be the last instruction in the IT block.
• Rt can be SP for word stores only
• Rt must not be PC
• Rn must not be PC
• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
[Rn, #offset]!
[Rn], #offset
shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
Immediate offset
− 255 to 4095
multiple of 4 in the
range − 1020 to
1020
“Address alignment” on page
Pre-indexed
− 255 to 255
multiple of 4 in the
range − 1020 to
1020
83.
Post-indexed
− 255 to 255
multiple of 4 in the
range − 1020 to
1020
6500C–ATARM–8-Feb-11