ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 913

IC MCU 32BIT 64KB FLASH 64LQFP

ATSAM3S1BA-AU

Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Datasheets

Specifications of ATSAM3S1BA-AU

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S1BA-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATSAM3S1BA-AUR
Manufacturer:
Atmel
Quantity:
10 000
36.7.33
Name:
Addresses:
Access:
This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match.
Only the first 16 bits (channel counter size) of field CV
• CVUPD: Comparison x Value Update
Define the comparison x value to be compared with the counter of the channel 0.
• CVMUPD: Comparison x Value Mode Update
0 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
incrementing.
1 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
decrementing.
Note:
CAUTION: to be taken into account, the write of the register PWM_CMPxVUPD must be followed by a write of the register
PWM_CMPxMUPD.
6500C–ATARM–8-Feb-11
31
23
15
7
This bit is useless if the counter of the channel 0 is left aligned (CALG = 0 in
PWM Comparison x Value Update Register
30
22
14
PWM_CMPxVUPD
0x40020134 [0], 0x40020144 [1], 0x40020154 [2], 0x40020164 [3], 0x40020174 [4], 0x40020184 [5],
0x40020194 [6], 0x400201A4 [7]
6
Write-only
29
21
13
5
28
20
12
4
UPD
CVUPD
CVUPD
CVUPD
are significant.
27
19
11
3
“PWM Channel Mode Register” on page
26
18
10
2
SAM3S Preliminary
25
17
9
1
CVMUPD
24
16
916)
8
0
913

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