ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 57

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.5.4
10.5.4.1
10.5.4.2
10.5.4.3
6500C–ATARM–8-Feb-11
Software ordering of memory accesses
DMB
DSB
ISB
Table 10-5.
1.
2.
The order of instructions in the program flow does not always guarantee the order of the corre-
sponding memory transactions. This is because:
“Memory system ordering of memory accesses” on page 55
memory system guarantees the order of memory accesses. Otherwise, if the order of memory
accesses is critical, software must include memory barrier instructions to force that ordering. The
processor provides the following memory barrier instructions:
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions com-
plete before subsequent memory transactions. See
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transac-
tions complete before subsequent instructions execute. See
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory
transactions is recognizable by subsequent instructions. See
Use memory barrier instructions in, for example:
Address range
0x60000000-
0x7FFFFFFF
0x80000000-
0x9FFFFFFF
0xA0000000-
0xBFFFFFFF
0xC0000000-
0xDFFFFFFF
0xE0000000-
0xE00FFFFF
0xE0100000-
0xFFFFFFFF
• the processor can reorder some memory accesses to improve efficiency, providing this does
• the processor has multiple bus interfaces
• memory or devices in the memory map have different wait states
• some memory accesses are buffered or speculative.
• MPU programming:
not affect the behavior of the instruction sequence.
– Use a DSB instruction to ensure the effect of the MPU takes place immediately at
the end of context switching.
See
The Peripheral and Vendor-specific device regions have no additional access constraints.
“Memory regions, types and attributes” on page 54
Memory region share ability policies (Continued)
Memory region
External RAM
External device
Private Peripheral
Bus
Vendor-specific
device
(2)
Memory type
Normal
Device
Strongly-
ordered
Device
“DMB” on page
(1)
(1)
(1)
(1)
for more information.
SAM3S Preliminary
“DSB” on page
“ISB” on page
describes the cases where the
Shareability
-
Shareable
Non-
shareable
Shareable
-
140.
(1)
(1)
(1)
142.
141.
WBWA
WT
-
-
-
(2)
(2)
57