ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 987

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
If ANACH is set in ADC_MR the ADC can apply different gain and offset on each channel. Oth-
erwise the parameters of CH0 are applied to all channels.
The gain is configurable through the GAIN bit of the Channel Gain Register (ADC_CGR) as
shown in
Table 39-6.
To allow full range, analog offset of the ADC can be configured by the OFFSET bit of the Chan-
nel Offset Register (ADC_COR). The Offset is only available in Single Ended Mode.
Table 39-7.
OFFSET Bit
GAIN<0:1>
Table
00
01
10
11
0
1
Gain of the Sample and Hold Unit: GAIN Bits and DIFF Bit.
Offset of the Sample and Hold Unit: OFFSET DIFF and Gain (G)
39-6.
OFFSET (DIFF = 0)
GAIN (DIFF = 0)
(G-1)Vrefin/2
1
1
2
4
0
SAM3S Preliminary
SAM3S Preliminary
OFFSET (DIFF = 1)
GAIN (DIFF = 1)
0.5
1
2
2
0
987
987