ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 170

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.21.5
• TBLOFF
Vector table base offset field. It contains bits[29:7] of the offset of the table base from the bottom of the memory map.
Bit[29] determines whether the vector table is in the code or SRAM memory region:
0 = code
1 = SRAM.
Bit[29] is sometimes called the TBLBASE bit.
When setting TBLOFF, you must align the offset to the number of exception entries in the vector table. The minimum align-
ment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the alignment by rounding up to the next power
of two. For example, if you require 21 interrupts, the alignment must be on a 64-word boundary because the required table
size is 37 words, and the next power of two is 64.
Table alignment requirements mean that bits[6:0] of the table offset are always zero.
170
TBLOFF
31
23
15
7
SAM3S Preliminary
Vector Table Offset Register
Reserved
30
22
14
6
The VTOR indicates the offset of the vector table base address from memory address
0x00000000. See the register summary in
The bit assignments are:
29
21
13
5
28
20
12
4
TBLOFF
TBLOFF
Reserved
27
19
11
3
Table 10-30 on page 164
TBLOFF
26
18
10
2
for its attributes.
25
17
9
1
6500C–ATARM–8-Feb-11
24
16
8
0