ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 873
![IC MCU 32BIT 64KB FLASH 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATSAM3S1BA-AU
Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S1BA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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36.6.5.4
6500C–ATARM–8-Feb-11
Changing the Synchronous Channels Update Period
It is possible to change the update period of synchronous channels while they are enabled. (See
“Method 2: Manual write of duty-cycle values and automatic trigger of the update” on page 862
and
page
To prevent an unexpected update of the synchronous channels registers, the user must use the
“PWM Sync Channels Update Period Update Register”
update period of synchronous channels while they are still enabled. This register holds the new
value until the end of the update period of synchronous channels (when UPRCNT is equal to
UPR in
rent PWM period, then updates the value for the next period.
Note:
Note:
Figure 36-18. Synchronized Update of Update Period Value of Synchronous Channels
“Method 3: Automatic write of duty-cycle values and automatic trigger of the update” on
864.)
“PWM Sync Channels Update Period Register”
If the update register PWM_SCUPUPD is written several times between two updates, only the last
written value is taken into account.
Changing the update period does make sense only if there is one or more synchronous channels
and if the update method 1 or 2 is selected (UPDM = 1 or 2 in
ter”
).
End of PWM period and
end of Update Period
of Synchronous Channels
PWM_SCUPUPD Value
User's Writing
PWM_SCUP
(PWM_SCUP)) and the end of the cur-
SAM3S Preliminary
(PWM_SCUPUPD) to change the
“PWM Sync Channels Mode Regis-
873
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