ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 432

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26.8
26.9
26.10 Programmable Clock Output Controller
432
Peripheral Clock Controller
Free Running Processor Clock
SAM3S Preliminary
The Power Management Controller controls the clocks of each embedded peripheral by means
of the Peripheral Clock Controller. The user can individually enable and disable the Clock on the
peripherals.
The user can also enable and disable these clocks by writing Peripheral Clock Enable 0
(PMC_PCER0), Peripheral Clock Disable 0 (PMC_PCDR0), Peripheral Clock Enable 1
(PMC_PCER1) and Peripheral Clock Disable 1 (PMC_PCDR1) registers. The status of the
peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR0) and
Peripheral Clock Status Register (PMC_PCSR1).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are
automatically disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral
has executed its last programmed operation before disabling the clock. This is to avoid data cor-
ruption or erroneous behavior of the system.
The bit number within the Peripheral Clock Control registers (PMC_PCER0-1, PMC_PCDR0-1,
and PMC_PCSR0-1) is the Peripheral Identifier defined at the product level. The bit number cor-
responds to the interrupt source number assigned to the peripheral.
The Free running processor clock (FCLK) used for sampling interrupts and clocking debug
blocks ensures that interrupts can be sampled, and sleep events can be traced, while the pro-
cessor is sleeping. It is connected to Master Clock (MCK).
The PMC controls 3 signals to be output on external pins, PCKx. Each signal can be indepen-
dently programmed via the PMC_PCKx registers.
PCKx can be independently selected between the Slow Clock (SLCK), the Main Clock
(MAINCK), the PLLA Clock (PLLACK), the PLLB Clock (PLLBCK) and the Master Clock (MCK)
by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2
between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of
PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks
are given in the PCKx bits of PMC_SCSR (System Clock Status Register).
Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actu-
ally what has been programmed in the Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching
clocks, it is strongly recommended to disable the Programmable Clock before any configuration
change and to re-enable it after the change is actually performed.
6500C–ATARM–8-Feb-11