ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 966

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

38.6
38.6.1
38.6.2
38.6.3
38.6.4
38.6.5
966
Functional Description
SAM3S Preliminary
ACC Description
Analog Settings
Write Protection System
Automatic Output Masking Period
Fault Mode
The Analog Comparator Controller mainly controls the analog comparator settings. There is also
post processing of the analog comparator output.
The output of the analog comparator is masked for the time the output may be invalid. This situ-
ation is encountered as soon as the analog comparator settings are modified.
A comparison flag is triggered by an event on the output of the analog comparator and an inter-
rupt can be generated accordingly. The event on the analog comparator output can be selected
among falling edge, rising edge or any edge.
The registers for programming are listed in
The user can select the input hysteresis and configure high-speed or low-speed options.
In order to provide security to the Analog Comparator Controller, a write protection system has
been implemented.
The write protection mode prevents writing
ter. When this mode is enabled and one of the protected registers is written, the register write
request is canceled.
Due to the nature of the write protection feature, enabling and disabling the write protection
mode requires a security code. Thus when enabling or disabling the write protection mode, the
WPKEY field of the ACC_WPMR register must be filled with the “ACC” ASCII code (correspond-
ing to 0x414343), otherwise the register write will be canceled.
As soon as the analog comparator settings change, the output is invalid for a duration depend-
ing on ISEL current.
A masking period is automatically triggered as soon as a write access is performed on ACC_MR
or ACC_ACR registers (whatever the register data content).
When ISEL = 0, the mask period is 8*tMCK, else 128*tMCK.
The masking period is reported by reading a negative value (bit 31 set) on ACC_ISR register
The FAULT output can be used to propagate a comparison match and act immediately via com-
binatorial logic by using the FAULT output which is directly connected to the FAULT input of the
PWM.
The source of the FAULT output can be configured to be either a combinational value derived
from the analog comparator output or the MCK resynchronized value (Refer to
”Analog Comparator Controller Block
• shortest propagation delay/highest current consumption
• longest propagation delay/lowest current consumption
Diagram”).
ACC Mode Register
Table 38-3 on page
967.
and
ACC Analog Control Regis-
6500C–ATARM–8-Feb-11
Figure 38-1