ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 272

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.4.2
16.4.3
272
SAM3S Preliminary
Slow Clock Generator
Voltage Regulator Control/Backup Low Power Mode
The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power
supply. As soon as the VDDIO is supplied, both the crystal oscillator and the embedded RC
oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow
clock to be valid in a short time (about 100 µs).
The user can select the crystal oscillator to be the source of the slow clock, as it provides a more
accurate frequency. The command is made by writing the Supply Controller Control Register
(SUPC_CR) with the XTALSEL bit at 1.This results in a sequence which first configures the PIO
lines multiplexed with XIN32 and XOUT32 to be driven by the oscillator, then enables the crystal
oscillator. then waits for 32,768 slow clock cycles, then switches the slow clock on the output of
the crystal oscillator and then disables the RC oscillator to save power. The switch of the slow
clock source is glitch free. The OSCSEL bit of the Supply Controller Status Register (SUPC_SR)
allows knowing when the switch sequence is done.
Coming back on the RC oscillator is only possible by shutting down the VDDIO power supply.
If the user does not need the crystal oscillator, the XIN32 and XOUT32 pins should be left
unconnected.
The user can also set the crystal oscillator in bypass mode instead of connecting a crystal. In
this case, the user has to provide the external clock signal on XIN32. The input characteristics of
the XIN32 pin are given in the product electrical characteristics section. In order to set the
bypass mode, the OSCBYPASS bit of the Supply Controller Mode Register (SUPC_MR) needs
to be set at 1.
The Supply Controller can be used to control the embedded 1.8V voltage regulator.
The voltage regulator automatically adapts its quiescent current depending on the required load
current. Please refer to the electrical characteristics section.
The programmer can switch off the voltage regulator, and thus put the device in Backup mode,
by writing the Supply Controller Control Register (SUPC_CR) with the VROFF bit at 1.
This can be done also by using WFE (Wait for Event) Cortex-M3 instruction with the deep mode
bit set to 1.
The Backup mode can also be entered by executing the WFI (Wait for Interrupt) or WFE (Wait for
Event) Cortex-M3 instructions. To select the Backup mode entry mechanism, two options are
available, depending on the SLEEPONEXIT bit in the Cortex-M3 System Control register:
This asserts the vddcore_nreset signal after the write resynchronization time which lasts, in the
worse case, two slow clock cycles. Once the vddcore_nreset signal is asserted, the processor
and the peripherals are stopped one slow clock cycle before the core power supply shuts off.
When the user does not use the internal voltage regulator and wants to supply VDDCORE by an
external supply, it is possible to disable the voltage regulator. Note that it is different from the
Backup mode. Depending on the application, disabling the voltage regulator can reduce power
consumption as the voltage regulator input (VDDIN) is shared with the ADC and DAC. This is
done through ONREG bit in SUPC_MR.
• Sleep-now: if the SLEEPONEXIT bit is cleared, the device enters Backup mode as soon as
• Sleep-on-exit: if the SLEEPONEXIT bit is set when the WFI instruction is executed, the
the WFI or WFE instruction is executed.
device enters Backup mode as soon as it exits the lowest priority ISR.
6500C–ATARM–8-Feb-11