ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 623

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 31-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 31-12. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
31.8.6.2
31.8.7
6500C–ATARM–8-Feb-11
TWD
TWD
TWD
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
Using the Peripheral DMA Controller (PDC)
S
S
S
10-bit Slave Addressing
DADR
DADR
DADR
DADR
DADR
DADR
W
W
W
For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and
set the other slave address bits in the internal address register (TWI_IADR). The two remaining
Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave
Addressing.
Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
Figure 31-13
the use of internal addresses to access the device.
Figure 31-13. Internal Address Usage
The use of the PDC significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequences:
1. Program IADRSZ = 1,
2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit
W
W
W
A
A
A
address)
IADR(23:16)
A
A
A
IADR(15:8)
IADR(7:0)
below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates
IADR(23:16)
IADR(15:8)
IADR(7:0)
S
T
A
R
T
M
S
B
Address
Device
A
A
A
0
IADR(15:8)
Sr
IADR(7:0)
A
A
A
S
B
L
W
W
R
E
R
T
I
/
DADR
A
C
K
WORD ADDRESS
IADR(15:8)
IADR(7:0)
M
S
B
DATA
FIRST
A
A
R
Sr
IADR(7:0)
A
C
A
A
A
A
K
WORD ADDRESS
DADR
SECOND
IADR(7:0)
P
DATA
DATA
A
SAM3S Preliminary
L
S
B
Sr
R
A
C
K
A
A
N
A
DADR
DATA
DATA
P
P
DATA
DATA
A
C
K
R
N
S
O
P
T
P
N
A
A
P
P
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