ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 926

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

37.3
Figure 37-1. Block Diagram
37.3.1
926
MCK
UDPCK
udp_int
external_resume
Block Diagram
SAM3S Preliminary
Atmel Bridge
MCU
APB
Signal Description
Bus
to
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by
reading and writing 8-bit values to APB registers.
The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain
(MCK) and a 48 MHz clock (UDPCK) used by the 12 MHz domain.
A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).
The signal external_resume is optional. It allows the UDP peripheral to wake up once in system
mode. The host is then notified that the device asks for a resume. This optional feature must
also be negotiated with the host during the enumeration.
Table 37-2.
Signal Name
UDPCK
MCK
udp_int
DDP
DDM
U
e
n
e
a
e
s
c
r
I
t
r
f
Signal Names
W
a
p
p
e
Master Clock
Domain
r
r
USB Device
RAM
FIFO
Dual
Port
Description
48 MHz clock
Master clock
Interrupt line connected to the Advanced Interrupt
Controller (AIC)
USB D+ line
USB D- line
Recovered 12 MHz
Domain
W
a
p
p
e
r
r
Suspend/Resume Logic
12 MHz
Interface
Engine
Serial
SIE
txoen
eopn
txd
rxdm
rxd
rxdp
6500C–ATARM–8-Feb-11
Transceiver
Embedded
Type
input
input
input
I/O
I/O
USB
DM
DP