ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 977

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

39. Analog-to-digital Converter (ADC)
39.1
39.2
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Description
Embedded Characteristics
The ADC is based on a 12-bit Analog-to-Digital Converter (ADC) managed by an ADC Control-
ler. Refer to the Block Diagram:
making possible the analog-to-digital conversions of 16 analog lines. The conversions extend
from 0V to ADVREF. The ADC supports an 10-bit or 12-bit resolution mode, and conversion
results are reported in a common register for all channels, as well as in a channel-dedicated reg-
ister. Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from
Timer Counter output(s) are configurable.
The comparison circuitry allows automatic detection of values below a threshold, higher than a
threshold, in a given range or outside the range, thresholds and ranges being fully configurable.
The ADC Controller internal fault output is directly connected to PWM Fault input. This input can
be asserted by means of comparison circuitry in order to immediately put the PWM outputs in a
safe state (pure combinational path).
The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC
channel. These features reduce both power consumption and processor intervention.
This ADC has a selectable single-ended or fully differential input and benefits from a 2-bit pro-
grammable gain. A whole set of reference voltages is generated internally from a single external
reference voltage node that may be equal to the analog supply voltage. An external decoupling
capacitance is required for noise filtering.
A digital error correction circuit based on the multi-bit redundant signed digit (RSD) algorithm is
employed in order to reduce INL and DNL errors.
Finally, the user can configure ADC timings, such as Startup Time and Tracking Time.
• 10/12-bit Resolution
• 1 MHz Conversion Rate
• Wide Range Power Supply Operation
• Selectable Single Ended or Differential Input Voltage
• Programmable Gain For Maximum Full Scale Input Range 0 - VDD
• Integrated Multiplexer Offering Up to 16 Independent Analog Inputs
• Individual Enable and Disable of Each Channel
• Hardware or Software Trigger
• Drive of PWM Fault Input
• PDC Support
• Possibility of ADC Timings Configuration
• Two Sleep Modes and Conversion Sequencer
– External Trigger Pin
– Timer Counter Outputs (Corresponding TIOA Trigger)
– PWM Event Line
Figure
39-1. It also integrates a 16-to-1 analog multiplexer,
SAM3S Preliminary
SAM3S Preliminary
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