ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 492

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 28-8. Input Change Interrupt Timings if there are no Additional Interrupt Modes
28.5.11
28.5.12
28.5.13
28.5.13.1
28.5.13.2
492
492
Read PIO_ISR
Pin Level
PIO_ISR
SAM3S Preliminary
SAM3S Preliminary
MCK
I/O Lines Lock
Programmable Schmitt Trigger
Parallel Capture Mode
Overview
Functional Description
The other lines are configured in Falling Edge or Low Level detection by default, if they have not
been previously configured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low
Level detection by writing 32’h0000_004A in PIO_FELLSR.
When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller
PWM), it can become locked by the action of this peripheral via an input of the PIO controller.
When an I/O line is locked, the write of the corresponding bit in the registers PIO_PER,
PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER, PIO_ABCDSR1 and
PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime
which I/O line is locked by reading the PIO Lock Status register PIO_LOCKSR. Once an I/O line
is locked, the only way to unlock it is to apply a hardware reset to the PIO Controller.
It is possible to configure each input for the Schmitt Trigger. By default the Schmitt trigger is
active. Disabling the Schmitt Trigger is requested when using the QTouch
The PIO Controller integrates an interface able to read data from a CMOS digital image sensor,
a high-speed parallel ADC, a DSP synchronous port in synchronous mode, etc.... For better
understanding and to ease reading, the following description uses an example with a CMOS dig-
ital image sensor.
The CMOS digital image sensor provides a sensor clock, an 8-bit data synchronous with the
sensor clock, and two data enables which are synchronous with the sensor clock too.
APB Access
APB Access
™
Library.
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11