ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 750

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

34.6.4
34.6.5
34.6.6
750
SAM3S Preliminary
Clock Control
TC Operating Modes
Trigger
The clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped. See
•
•
Figure 34-4. Clock Control
Each channel can independently operate in two different modes:
•
•
The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register.
In Capture Mode, TIOA and TIOB are configured as inputs.
In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not
selected to be the external trigger.
A trigger resets the counter and starts the counter clock. Three types of triggers are common to
both modes, and a fourth external trigger is available to each mode.
The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS
commands in the Control Register. In Capture Mode it can be disabled by an RB load event
if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare
event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no
effect: only a CLKEN command in the Control Register can re-enable the clock. When the
clock is enabled, the CLKSTA bit is set in the Status Register.
The clock can also be started or stopped: a trigger (software, synchro, external or compare)
always starts the clock. The clock can be stopped by an RB load event in Capture Mode
(LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in
TC_CMR). The start and the stop commands have effect only if the clock is enabled.
Capture Mode provides measurement on signals.
Waveform Mode provides wave generation.
Selected
Counter
Clock
Clock
Figure
Q
34-4.
R
S
Trigger
CLKSTA
Q
CLKEN
S
R
Event
Stop
CLKDIS
Disable
Event
6500C–ATARM–8-Feb-11