ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 110

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.13.3
10.13.3.1
10.13.3.2
10.13.3.3
10.13.3.4
110
SAM3S Preliminary
ASR, LSL, LSR, ROR, and RRX
Syntax
Operation
Restrictions
Condition flags
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with
Extend.
where:
op
S
result of the operation, see
Rd
Rm
Rs
significant byte is used and can be in the range 0 to 255.
n
MOV{S}{cond} Rd, Rm is the preferred syntax for LSL{S}{cond} Rd, Rm, #0.
ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of
places specified by constant n or register Rs.
RRX moves the bits in register Rm to the right by 1.
In all these instructions, the result is written to Rd, but the value in register Rm remains
unchanged. For details on what result is generated by the different instructions, see
ations” on page
Do not use SP and do not use PC.
If S is specified:
• these instructions update the N and Z flags according to the result
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
ASR
LSL
LSR
ROR
ASR
LSL
LSR
ROR
is one of:
Arithmetic Shift Right.
Logical Shift Left.
Logical Shift Right.
Rotate Right.
is an optional suffix. If S is specified, the condition code flags are updated on the
is the destination register.
is the register holding the value to be shifted.
is the register holding the shift length to apply to the value in Rm. Only the least
is the shift length. The range of shift length depends on the instruction:
shift length from 1 to 32
shift length from 0 to 31
shift length from 1 to 32
shift length from 1 to 31.
81.
“Conditional execution” on page
84.
6500C–ATARM–8-Feb-11
“Shift Oper-