ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 493

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 28-9. PIO controller connection with CMOS digital image sensor
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
PDC
As soon as the parallel capture mode is enabled by writing the PCEN bit at 1 in PIO_PCMR
(“PIO Parallel Capture Mode Register”
CLK), the sensor data (PIODC[7:0]) and the sensor data enable signals (PIODCEN1 and
PIODCEN2) are configured automatically as INPUTS. To know which I/O lines are associated
with the sensor clock, the sensor data and the sensor data enable signals, refer to the I/O multi-
plexing table(s) in the product datasheet.
Once it is enabled, the parallel capture mode samples the data at rising edge of the sensor clock
and resynchronizes it with the PIO clock domain.
The size of the data which can be read in PIO_PCRHR
ing Register”
larger than 8 bits, then the parallel capture mode samples several sensor data to form a concat-
enated data of size defined by DSIZE. Then this data is stored in PIO_PCRHR and the flag
DRDY is set to 1 in PIO_PCISR
The parallel capture mode can be associated with a reception channel of the Peripheral DMA
Controller (PDC). This enables performing reception transfer from parallel capture mode to a
memory buffer without any intervention from the CPU. Transfer status signals from PDC are
available in PIO_PCISR through the flags ENDRX and RXBUFF (see
Interrupt Status Register” on page
The parallel capture mode can take into account the sensor data enable signals or not. If the bit
ALWYS is set to 0 in PIO_PCMR, the parallel capture mode samples the sensor data at the ris-
ing edge of the sensor clock only if both data enable signals are active (at 1). If the bit ALWYS is
set to 1, the parallel capture mode samples the sensor data at the rising edge of the sensor
clock whichever the data enable signals are.
The parallel capture mode can sample the sensor data only one time out of two. This is particu-
larly useful when the user wants only to sample the luminance Y of a CMOS digital image sensor
which outputs a YUV422 data stream. If the HALFS bit is set to 0 in PIO_PCMR, the parallel
capture mode samples the sensor data in the conditions described above. If the HALFS bit is set
to 1 in PIO_PCMR, the parallel capture mode samples the sensor data in the conditions
described above, but only one time out of two. Depending on the FRSTS bit in PIO_PCMR, the
sensor can either sample the even or odd sensor data. If sensor data are numbered in the order
that they are received with an index from 0 to n, if FRSTS = 0 then only data with an even index
are sampled, if FRSTS = 1 then only data with an odd index are sampled. If data is ready in
Data
Status
) can be programmed thanks to the DSIZE field in PIO_PCMR. If this data size is
PIO Controller
Parallel Capture
Mode
(“PIO Parallel Capture Interrupt Status Register”
PIODC[7:0]
PIODCCLK
PIODCEN2
PIODCEN1
534).
), the I/O lines connected to the sensor clock (PIODC-
(“PIO Parallel Capture Reception Hold-
SAM3S Preliminary
SAM3S Preliminary
PCLK
DATA[7:0]
VSYNC
HSYNC
Image Sensor
CMOS Digital
“PIO Parallel Capture
).
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