ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 591

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 30-9. Programmable Delays
30.7.3.5
30.7.3.6
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Chip Select 1
Chip Select 2
SPI Peripheral DMA Controller (PDC)
Peripheral Selection
SPCK
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus
release time.
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By
default, all the NPCS signals are high before and after each transfer.
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In
this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the
SPI_TDR has no effect.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is
used to select the current peripheral. This means that the peripheral selection can be defined for
each new data. The value to write in the SPI_TDR register as the following format.
[xxxxxxx(7-bit) + LASTXFER(1-bit)
equals to the chip select to assert as defined in
LASTXFER bit at 0 or 1 depending on CSAAT bit.
Note:
CSAAT, LASTXFER and CSNAAT bits are discussed in
tion with PDC”
If LASTXFER is used, the command must be issued before writing the last character. Instead of
LASTXFER, the user can use the SPIDIS command. After the end of the PDC transfer, wait for
the TXEMPTY flag, then write SPIDIS into the SPI_CR register (this will not change the configu-
ration register values); the NPCS will be deactivated after the last character transfer. Then,
another PDC transfer can be started if the SPIEN was previously written in the SPI_CR register.
In both fixed and variable mode the Peripheral DMA Controller (PDC) can be used to reduce
processor overhead.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is
an optimal means, as the size of the data transfer between the memory and the SPI is either 8
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
• Variable Peripheral Select: Data can be exchanged with more than one peripheral without
having to reprogram the NPCS field in the SPI_MR register.
1. Optional.
DLYBCS
.
DLYBS
()
+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS
Section 30.8.4
DLYBCT
Section 30.7.3.9 ”Peripheral Deselec-
SAM3S Preliminary
SAM3S Preliminary
(SPI Transmit Data Register) and
DLYBCT
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