ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 164

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.21 System control block
Table 10-30. Summary of the system control block registers
Notes:
10.21.1
164
Address
0xE000E008
0xE000ED00
0xE000ED04
0xE000ED08
0xE000ED0C
0xE000ED10
0xE000ED14
0xE000ED18
0xE000ED1C
0xE000ED20
0xE000ED24
0xE000ED28
0xE000ED28
0xE000ED29
0xE000ED2A
0xE000ED2C
0xE000ED34
0xE000ED38
1. See the register description for more information.
2. A subregister of the CFSR.
SAM3S Preliminary
The CMSIS mapping of the Cortex-M3 SCB registers
Name
ACTLR
CPUID
ICSR
VTOR
AIRCR
SCR
CCR
SHPR1
SHPR2
SHPR3
SHCRS
CFSR
MMSR
BFSR
UFSR
HFSR
MMAR
BFAR
(2)
(2)
(2)
The System control block (SCB) provides system implementation information, and system con-
trol. This includes configuration, control, and reporting of the system exceptions. The system
control block registers are:
To improve software efficiency, the CMSIS simplifies the SCB register presentation. In the
CMSIS, the byte array SHP[0] to SHP[12] corresponds to the registers SHPR1-SHPR3.
Type
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
(1)
(1)
Required
privilege
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Reset
value
0x00000000
0x412FC230
0x00000000
0x00000000
0xFA050000
0x00000000
0x00000200
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00
0x00
0x0000
0x00000000
Unknown
Unknown
Description
“Auxiliary Control Register” on page 165
“CPUID Base Register” on page 166
“Interrupt Control and State Register” on page 167
“Vector Table Offset Register” on page 170
“Application Interrupt and Reset Control Register” on page
171
“System Control Register” on page 173
“Configuration and Control Register” on page 174
“System Handler Priority Register 1” on page 177
“System Handler Priority Register 2” on page 178
“System Handler Priority Register 3” on page 178
“System Handler Control and State Register” on page 179
“Configurable Fault Status Register” on page 181
“Memory Management Fault Address Register” on page
188
“Bus Fault Status Register” on page 183
“Usage Fault Status Register” on page 185
“Hard Fault Status Register” on page 187
“Memory Management Fault Address Register” on page
188
“Bus Fault Address Register” on page 189
6500C–ATARM–8-Feb-11