ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 497

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

28.5.14
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Write Protection Registers
To prevent any single software error that may corrupt PIO behavior, certain address spaces can
be write-protected by setting the WPEN bit in the
(PIO_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Pro-
tect Status Register (PIO_WPSR) is set and the field WPVSRC indicates in which register the
write access has been attempted.
The WPVS flag is reset by writing the PIO Write Protect Mode Register (PIO_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
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“PIO Enable Register” on page 502
“PIO Disable Register” on page 502
“PIO Output Enable Register” on page 503
“PIO Output Disable Register” on page 504
“PIO Input Filter Enable Register” on page 505
“PIO Input Filter Disable Register” on page 505
“PIO Multi-driver Enable Register” on page 510
“PIO Multi-driver Disable Register” on page 511
“PIO Pull Up Disable Register” on page 512
“PIO Pull Up Enable Register” on page 512
“PIO Peripheral ABCD Select Register 1” on page 514
“PIO Peripheral ABCD Select Register 2” on page 515
“PIO Output Write Enable Register” on page 520
“PIO Output Write Disable Register” on page 520
“PIO Pad Pull Down Disable Register” on page 518
“PIO Pad Pull Down Status Register” on page 519
“PIO Parallel Capture Mode Register” on page 530
“PIO Write Protect Mode Register”
SAM3S Preliminary
SAM3S Preliminary
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