ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 937

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 37-11. Data OUT Transfer for Ping-pong Endpoint
Note:
37.6.2.4
6500C–ATARM–8-Feb-11
USB Bus
Packets
RX_DATA_BK0 Flag
(UDP_CSRx)
RX_DATA_BK1 Flag
(UDP_CSRx)
FIFO (DPR)
Bank 0
FIFO (DPR)
Bank 1
An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set.
Stall Handshake
Host Sends First Data Payload
Data OUT
PID
Set by USB Device,
Data Payload Written
in FIFO Endpoint Bank 0
Write by USB Device
Data OUT1
Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine
which one to clear first. Thus the software must keep an internal counter to be sure to clear alter-
natively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software
application is busy elsewhere and the two banks are filled by the USB host. Once the application
comes back to the USB driver, the two flags are set.
A stall handshake can be used in one of two distinct occasions. (For more information on the
stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.)
The following procedure generates a stall packet:
11. The microcontroller notifies the USB device it has finished the transfer by clearing
12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO
• A functional stall is used when the halt feature associated with the endpoint is set. (Refer to
• To abort the current request, a protocol stall is used, but uniquely with control transfer.
1. The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint’s register.
2. The host receives the stall packet.
Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt
feature.)
RX_DATA_BK1 in the endpoint’s UDP_CSRx register.
Bank 0.
Data OUT 1
ACK
PID
Read By Microcontroller
Set by USB Device,
Data Payload Written
in FIFO Endpoint Bank 1
Interrupt Pending
Microcontroller Reads Data 1 in Bank 0,
Host Sends Second Data Payload
Data OUT 1
Data OUT
PID
Write by USB Device
Data OUT 2
Data OUT 2
Cleared by Firmware
ACK
PID
SAM3S Preliminary
Read By Microcontroller
Microcontroller Reads Data2 in Bank 1,
Host Sends Third Data Payload
Data OUT
PID
Interrupt Pending
Data OUT 2
Write In Progress
Cleared by Firmware
Data OUT 3
Data OUT 3
A
P
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