ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 801

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

35.8
35.8.1
6500C–ATARM–8-Feb-11
High Speed MultiMedia Card Operations
Command - Response Operation
After a power-on reset, the cards are initialized by a special message-based High Speed Multi-
Media Card bus protocol. Each message is represented by one of the following tokens:
Card addressing is implemented using a session address assigned during the initialization
phase by the bus controller to all currently connected cards. Their unique CID number identifies
individual cards.
The structure of commands, responses and data blocks is described in the High Speed MultiMe-
dia-Card System Specification. See also
High Speed MultiMediaCard bus data transfers are composed of these tokens.
There are different types of operations. Addressed operations always contain a command and a
response token. In addition, some operations have a data token; the others transfer their infor-
mation directly within the command or response structure. In this case, no data token is present
in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock
HSMCI Clock.
Two types of data transfer commands are defined:
Both read and write operations allow either single or multiple block transmission. A multiple
block transmission is terminated when a stop command follows on the CMD line similarly to the
sequential read or when a multiple block transmission has a pre-defined block count
Transfer Operation” on page
The HSMCI provides a set of registers to perform the entire range of High Speed MultiMedia
Card operations.
After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the
HSMCI_CR Control Register.
The PWSEN bit saves power by dividing the HSMCI clock by 2
inactive.
The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow
stopping the HSMCI Clock during read or write access if the internal FIFO is full. This will guar-
antee data integrity, not bandwidth.
All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMediaCard
System Specification.
• Command: A command is a token that starts an operation. A command is sent from the host
• Response: A response is a token which is sent from an addressed card or (synchronously)
• Data: Data can be transferred from the card to the host or vice versa. Data is transferred via
• Sequential commands: These commands initiate a continuous data stream. They are
• Block-oriented commands: These commands send a data block succeeded by CRC bits.
either to a single card (addressed command) or to all connected cards (broadcast
command). A command is transferred serially on the CMD line.
from all connected cards to the host as an answer to a previously received command. A
response is transferred serially on the CMD line.
the data line.
terminated only when a stop command follows on the CMD line. This mode reduces the
command overhead to an absolute minimum.
804.).
Table 35-6 on page
SAM3S Preliminary
802.
PWSDIV
+ 1 when the bus is
(See “Data
801